1. Field of the Invention
The present invention relates to analog VLSI circuitry, specifically compensated multipliers.
2. Art Background
The use of analog VLSI circuitry to implement functions traditionally performed with digital components is becoming more and more common. In addition, Analog VLSI is being used more frequently to model complex systems that are often simulated in software. For example, Mead has been a proponent of using analog VLSI to implement neural systems. See, Mead, Analog VLSI Neural Systems, (Addison Wesley, 1989). An important component of the work lies in the attempt to mimic the adaptation that real biological neurons are able to do. Therefore, modeling analog VLSI simulations of neural systems requires producing circuits that are intrinsically adaptive. Another component of this design philosophy is the exploration of architectures and circuits that are tolerant of device variations and perform computations collectively.
Other research is focused on increasing the accuracy and precision of computation with analog VLSI and on developing a design methodology for creating analog VLSI circuits which can be adjusted to perform to the desired accuracy. See, Kirk, Fleischer, Barr, and Watts, "Constrained Optimization Applied to the Parameter Setting Problem for Analog Circuits," IEEE Neural Information Processing Systems, 1991 (NIPS 91), (Morgan Kaufman, San Diego, 1991).
It is possible to make analog circuits more quantitatively useful by designing compensatable circuit building blocks that can be adjusted to perform more closely to some performance metric. An example is the CMOS amplifier with offset adaptation, U.S. Pat. No. 5,068,622, Mead, et al. Mead describes an integrated circuit amplifier having a random input offset voltage that is adaptable to cancel the input offset voltage. However, application of this concept to other types of devices is not straightforward. For example, an ideal linear differential multiplier produces the product P according to the following equation: EQU P=K(X-X.sub.0) (W-W.sub.0)
where X, X.sub.0, W, W.sub.0 are the four input parameters which form the two differential inputs (X-X.sub.0) and (W-W.sub.0). Implementation in analog VLSI, for example, as a two transistor differential multiplier shown in FIG. 1, will yield a less desirable function: EQU P=K.sub.2 (X-X.sub.0) (W-W.sub.0)+Q
where K.sub.2 is not a constant factor, but may be a function of the inputs, and Q is an additive offset, which also may be a function of the inputs. Thus, the offsets generated are dictated by at least four input parameters, which must be controlled in a coordinated fashion in order to achieve the desired output.